This invention relates generally to data storage systems, and more particularly to data storage systems having redundancy arrangements to protect against total system failure in the event of a failure in a component or subassembly of the storage system.
As is known in the art, large mainframe computer systems require large capacity data storage systems. These large host computer systems generally include data processors which perform many operations on data introduced to the computer system through peripherals including the data storage system. The results of these operations are output to peripherals, including the storage system.
One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the host frame computer system are coupled together through a system interface. The system interface includes xe2x80x9cfront endxe2x80x9d directors coupled to the host computer and xe2x80x9cback endxe2x80x9d disk directors coupled to the bank of disk drives. The system interface operates the directors in such a way that they are transparent to the computer. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the mainframe computer system merely thinks it is operating with one mainframe memory. One such system is described in U.S. Pat. 5,206,939, entitled xe2x80x9cSystem and Method for Disk Mapping and Data Retrievalxe2x80x9d, inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
As described in such U.S. Patent, the system interface may also include, in addition to the front end and back end directors, addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the host computer system before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the host computer. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
The front-end directors, back end directors and cache memory are interconnected through a backplane printed circuit board. More particularly, disk directors are mounted on disk director printed circuit boards. The front-end directors are mounted on front-end printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The back end director, front-end director and cache memory printed circuit boards plug into the backplane printed circuit board. In order to provide data integrity in case of a failure in a director, the backplane printed circuit board has a pair of buses. One set the disk directors is connected to one bus and another set of the disk directors is connected to the other bus. Likewise, one set the front-end directors is connected to one bus and another set of the front-end directors is connected to the other bus. The cache memories are connected to both buses. Each one of the buses provides data, address and control information.
Thus, the use of two, or more, buses provides a degree of redundancy to protect against a total system failure in the event that the directors, or disk drives connected to one bus fail. Further, the use of two, or more, buses increases the data transfer bandwidth of the system compared to a system having a single bus.
As is also known in the art, in one type of data storage system the system interface is coupled to a personal computer (PC). The PC is used for such things as testing the system and updating programs stored in the directors. The communications between the PC and the system interface uses microprocessors (i.e., central processing units (CPUs) in the directors. In order for the CPUs to perform their primary function, which is moving data between the host computer and the disk drives with maximum speed, it is desirable to reduce the time the required for the CPU to communicate with the PC.
In accordance with the present invention, a controller is provided for providing buffering between a data source/destination and a network. The network is coupled to the controller through an Ethernet bus. The controller includes an Ethernet MAC Core coupled to the Ethernet bus. A buffer is disposed between the MAC Core and the data source/destination for storing data/control frames. Each frame has an Ethernet packet data portion and an Ethernet MAC Core control signal portion. A control section enables the frames to pass between the source/destination and the network through the MAC Core under control of the buffer stored Core control signals portion of the packets independently of the operation of the central processing unit.
In accordance with one embodiment of the invention, a storage system is provided wherein a host computer is coupled to a bank of disk drives through a system interface. The system interface includes a memory. A plurality of directors controls data transfer between the host computer and the bank of disk drives as such data passes through the memory. Each one of the directors is in communication with the busses. Each one of the directors includes a controller is provided for providing buffering between a data source/destination and a network. The network is coupled to the controller through an Ethernet bus. The controller includes an Ethernet MAC Core coupled to the Ethernet bus. A buffer is disposed between the MAC Core and the data source/destination for storing data/control frames. Each frame has an Ethernet packet data portion and an Ethernet MAC Core control signal portion. A control section enables the packets to pass between the source/destination and the network through the MAC Core under control of the buffer stored Core control signals portion of the frames independently of the operation of the central processing unit.
With such an arrangement, the directors are able to perform their main task of controlling data flow between the host computer and the bank of disk drives while communication of such directors.